Auditeon

User Tools

Site Tools

Trace:
software:linux:jtag

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
software:linux:jtag [2013/04/29 01:10] – [TIAO USB Multi Protocol adapter JTAG] adminsoftware:linux:jtag [2015/10/11 20:03] (current) – [TIAO USB Multi Protocol adapter JTAG] admin
Line 312: Line 312:
 Unfortunately the output of this shows no success as it does at the OpenMoko board: Unfortunately the output of this shows no success as it does at the OpenMoko board:
   Found Generic flash chip "unknown SPI chip (RDID)" (0 kB, SPI).   Found Generic flash chip "unknown SPI chip (RDID)" (0 kB, SPI).
-Instead SPI2 at the TIAO tumpa board which is mapped to port B works better. Connections are: +Instead use SPI2 at the TIAO tumpa board, which is mapped to port B. This works fine. Connections are: 
-(SPI2->EEPROM) +^ SPI2 ^ EEPROM ^ 
-  * MISO->DO +| MISO  | DO  | 
-  * VCC ->VCC+/HOLD+/WP +| VCC  | VCC+/HOLD+/WP  | 
-  * SCK ->CLK +| SCK  | CLK  | 
-  * MOSI->DI +| MOSI  | DI  | 
-  * CS  ->/CS +| CS  | /CS  | 
-  * GND ->GND+| GND  | GND  |
  
 | {{ http://www.auditeon.com/xyz/auditeon/20130317_213801.IMG_0723.1024x796.jpg?385x300 |TIAO adapter with flash eeprom}} | | {{ http://www.auditeon.com/xyz/auditeon/20130317_213801.IMG_0723.1024x796.jpg?385x300 |TIAO adapter with flash eeprom}} |
Line 333: Line 333:
 Since the only difference between port A and port B is that port A has a 74LVC16T245 buffer IC driving the signals MOSI, CLK and CS via a 56 Ohm resistor, I started bypassing this buffer IC and tested if port A could behave like port B. I noticed then that for proper communication the only signal that had to be bypassed was the CLK signal. By connecting CLK directly to pin 16 (TCLK) of the FT2232HL, the communication worked fine. But as soon as the CLK signal would go via the buffer IC, the CLK output (LVC16T245, pin 2) signal would be degraded to such an extend that communication with the memory chip could not be established properly. After this I understood there is nothing wrong with the TIAO JTAG board.nor with the drivers. The root cause for this is a mismatch between the output impedance of the JTAG board and the relatively long (>20cm) cables. This effect plays a substantial role at high frequency signals, which this interface is running at. I measured a CLK signal of 30Mhz. A simple solution is to shorten the cables. Instead of 20cm I strongly advise to use not more than 10cm.\\  Since the only difference between port A and port B is that port A has a 74LVC16T245 buffer IC driving the signals MOSI, CLK and CS via a 56 Ohm resistor, I started bypassing this buffer IC and tested if port A could behave like port B. I noticed then that for proper communication the only signal that had to be bypassed was the CLK signal. By connecting CLK directly to pin 16 (TCLK) of the FT2232HL, the communication worked fine. But as soon as the CLK signal would go via the buffer IC, the CLK output (LVC16T245, pin 2) signal would be degraded to such an extend that communication with the memory chip could not be established properly. After this I understood there is nothing wrong with the TIAO JTAG board.nor with the drivers. The root cause for this is a mismatch between the output impedance of the JTAG board and the relatively long (>20cm) cables. This effect plays a substantial role at high frequency signals, which this interface is running at. I measured a CLK signal of 30Mhz. A simple solution is to shorten the cables. Instead of 20cm I strongly advise to use not more than 10cm.\\ 
 As an alternative, one could try to match the output impedance of the JTAG board by adding a resistor at the MOSI, CLK and CS signals of the memory IC, presuming the cable impedance has a identical value. There are several effects which cause the delay of the CLK signal. The buffer IC gives a delay of about 4ns, the 56 Ohm resistor causes a less steep transition and an extra signal delay through 20cm cable of about 1ns. This all must be taken into account.\\ Another good explanation and design guidelines for (ac) termination and cabling can be found [[http://www.actel.com/documents/APA_External_ISP_AN.pdf|here]].\\ \\  As an alternative, one could try to match the output impedance of the JTAG board by adding a resistor at the MOSI, CLK and CS signals of the memory IC, presuming the cable impedance has a identical value. There are several effects which cause the delay of the CLK signal. The buffer IC gives a delay of about 4ns, the 56 Ohm resistor causes a less steep transition and an extra signal delay through 20cm cable of about 1ns. This all must be taken into account.\\ Another good explanation and design guidelines for (ac) termination and cabling can be found [[http://www.actel.com/documents/APA_External_ISP_AN.pdf|here]].\\ \\ 
-Lowering the bus frequency, resulted in successful communication. This is clearly a hint that there are issues with signal integrity. With the following command this can be realized:+Lowering the bus frequency, resulted in successful communication. This is clearly a hint that there are issues with signal integrity. With the following command there is success:
   ./flashrom -p ft2232_spi:divisor=4,type=tumpa,port=A   ./flashrom -p ft2232_spi:divisor=4,type=tumpa,port=A
-To understand this issue better, an analysis of the cabling, termination and buffer circuit should be done. To make measuring easier one can use the following one-liner, which repeats activity on the bus:+The frequency of the CLK signal lowered, but not as expected.  
 +According to [[http://www.ftdichip.com/Support/Documents/AppNotes/AN_135_MPSSE_Basics.pdf|Application Note 135, MPSSE Basics of the FTDI documentation]] the frequency can be set with the following formula: 
 + 
 +  frequency = 60MHz /((1 + divisor)*2) 
 + 
 +The divisor is a 16-bit hex value between 0x0000 and 0xFFFF and represent the amount of 2 divisors which are chained. With a 60Mhz base clock, data rates range between 30MHz and ~460Hz and applies to the FT2232H, according to page 9 of AN 135. This formule will give the 16-bit divisor: 
 +  dwClockDivisor=(30000000/SCL_Frequency) - 1; // With SCL_Frequency in Hz. For example, an SCL_Frequency of 1 MHz will give a dwClockDivisor of 29. 
 +And code in Application note 114, page 7 and 8 to set the registers: 
 +<code c> 
 +... 
 +OutputBuffer[dwNumBytesToSend++] = '\x86'; //Command to set clock divisor 
 +OutputBuffer[dwNumBytesToSend++] = BYTE(dwClockDivisor & '\xFF'); //Set 0xValueL of clock divisor 
 +OutputBuffer[dwNumBytesToSend++] = BYTE(dwClockDivisor >> 8); //Set 0xValueH of clock divisor 
 +ftStatus = FT_Write(ftHandle, OutputBuffer, dwNumBytesToSend, &dwNumBytesSent); // Send out the commands 
 +dwNumBytesToSend = 0; //Clear output buffer 
 +... 
 +</code> 
 +This is rather confusing implemented in flashrom [[http://tracker.coreboot.org/trac/flashrom/changeset/1537|since May 16th 2012]]. Measurements when using divisor=2 or with no divisor arguments, show a CLK signal of 30 MHz (The comments in the code say 2 is a default value). The code seems differently written than FTDI did.\\ \\  
 +To make measurements easier one can use the following one-liner, which repeats the command and activity on the bus. With this it is easier to analyze the cabling, termination and buffer circuit:
   cd $HOME/devel/flashrom; while true; do ./flashrom -p ft2232_spi:divisor=4,type=tumpa,port=A; done   cd $HOME/devel/flashrom; while true; do ./flashrom -p ft2232_spi:divisor=4,type=tumpa,port=A; done
 ===== Intermezzo: Modifying find_all_pp ==== ===== Intermezzo: Modifying find_all_pp ====
Line 360: Line 378:
 In documentation about the output characteristics(([[http://www.idt.com/document/224-alvclvc-logic-characteristics-and-apps-0]], see page 9.)) of the LVC16 family, to which the 74LVC16T245 buffer IC belongs, the output impedance is about 15 Ohm. Rather than the previously used separate wires, a 1/20 inch flat cable was taken with following specifications: In documentation about the output characteristics(([[http://www.idt.com/document/224-alvclvc-logic-characteristics-and-apps-0]], see page 9.)) of the LVC16 family, to which the 74LVC16T245 buffer IC belongs, the output impedance is about 15 Ohm. Rather than the previously used separate wires, a 1/20 inch flat cable was taken with following specifications:
   * [[http://www.belden.com/products/catalogs/mastercatalog/brilliance/upload/07FlatCable-2.pdf|Belden AWM 2651]] See 7.5, characteristic impedance of 105 Ohm, Ground-Signal-Ground configuration. Total cable length: 20cm.   * [[http://www.belden.com/products/catalogs/mastercatalog/brilliance/upload/07FlatCable-2.pdf|Belden AWM 2651]] See 7.5, characteristic impedance of 105 Ohm, Ground-Signal-Ground configuration. Total cable length: 20cm.
-The flat cable was taken from an old computer diskette drive. It was not 100% clear whether the specifications from belden.com applied actually to this cable. Initially I thought the characteristic impedance was 90 Ohm. Measurements show the following:+The flat cable was taken from an old computer diskette drive. It was not 100% clear whether the specifications from belden.com applied actually to this cable. Initially I thought the characteristic impedance was 90 Ohm. With channel 1 showing the buffer input signal and channel 2 showing the cable end, measurements show the following:
 ^ {{ http://www.auditeon.com/xyz/auditeon/01.RS_82.RL_100.JPG?372x300 |RS=82, RL=100}} ^ {{ http://www.auditeon.com/xyz/auditeon/02.RS_82.RL_OO.JPG?372x300 |RS=82, RL=∞}} ^ {{ http://www.auditeon.com/xyz/auditeon/03.RS_82.RL_90.JPG?372x300 |RS=82, RL=90}} ^ {{ http://www.auditeon.com/xyz/auditeon/04.RS_75.RL_90.JPG?372x300 |RS=75, RL=90}} ^ ^ {{ http://www.auditeon.com/xyz/auditeon/01.RS_82.RL_100.JPG?372x300 |RS=82, RL=100}} ^ {{ http://www.auditeon.com/xyz/auditeon/02.RS_82.RL_OO.JPG?372x300 |RS=82, RL=∞}} ^ {{ http://www.auditeon.com/xyz/auditeon/03.RS_82.RL_90.JPG?372x300 |RS=82, RL=90}} ^ {{ http://www.auditeon.com/xyz/auditeon/04.RS_75.RL_90.JPG?372x300 |RS=75, RL=90}} ^
 |  RS=97 Ohm\\ Termination: 100 Ohm\\ Signal source cable: 0.5m  |  RS=97 Ohm\\ No termination\\ Signal source cable: 0.5m  |  RS=97 Ohm\\ Termination: 90 Ohm\\ Signal source cable: 0.5m  |  RS=90 Ohm\\ Termination 90 Ohm\\ Signal source cable: 1m  | |  RS=97 Ohm\\ Termination: 100 Ohm\\ Signal source cable: 0.5m  |  RS=97 Ohm\\ No termination\\ Signal source cable: 0.5m  |  RS=97 Ohm\\ Termination: 90 Ohm\\ Signal source cable: 0.5m  |  RS=90 Ohm\\ Termination 90 Ohm\\ Signal source cable: 1m  |
Line 384: Line 402:
 ^ {{ http://www.auditeon.com/xyz/auditeon/10.RS_90.RL_OO.flashrom_jtag_clk.JPG?372x300 |RS=105, RL=∞}} ^ ^ {{ http://www.auditeon.com/xyz/auditeon/10.RS_90.RL_OO.flashrom_jtag_clk.JPG?372x300 |RS=105, RL=∞}} ^
 |  Real clk signal\\ RS=105 Ohm\\ No termination\\ JTAG cable length: 20cm  | |  Real clk signal\\ RS=105 Ohm\\ No termination\\ JTAG cable length: 20cm  |
 +The LVC16T245 buffer is causing a delay of about 6ns for the CLK signal.
 ===== Links and information ===== ===== Links and information =====
   * [[http://blog.csdn.net/imalex/article/details/6719614]]   * [[http://blog.csdn.net/imalex/article/details/6719614]]
software/linux/jtag.1367190626.txt.gz · Last modified: 2013/04/29 01:10 by admin

Page Tools

Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Noncommercial-Share Alike 4.0 International
CC Attribution-Noncommercial-Share Alike 4.0 International Donate Powered by PHP Valid HTML5 Valid CSS Driven by DokuWiki