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software:linux:jtag [2013/05/19 00:40] – [TIAO USB Multi Protocol adapter JTAG] adminsoftware:linux:jtag [2015/10/11 20:03] (current) – [TIAO USB Multi Protocol adapter JTAG] admin
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 Unfortunately the output of this shows no success as it does at the OpenMoko board: Unfortunately the output of this shows no success as it does at the OpenMoko board:
   Found Generic flash chip "unknown SPI chip (RDID)" (0 kB, SPI).   Found Generic flash chip "unknown SPI chip (RDID)" (0 kB, SPI).
-Instead SPI2 at the TIAO tumpa board which is mapped to port B works better. Connections are: +Instead use SPI2 at the TIAO tumpa board, which is mapped to port B. This works fine. Connections are: 
-(SPI2->EEPROM) +^ SPI2 ^ EEPROM ^ 
-  * MISO->DO +| MISO  | DO  | 
-  * VCC ->VCC+/HOLD+/WP +| VCC  | VCC+/HOLD+/WP  | 
-  * SCK ->CLK +| SCK  | CLK  | 
-  * MOSI->DI +| MOSI  | DI  | 
-  * CS  ->/CS +| CS  | /CS  | 
-  * GND ->GND+| GND  | GND  |
  
 | {{ http://www.auditeon.com/xyz/auditeon/20130317_213801.IMG_0723.1024x796.jpg?385x300 |TIAO adapter with flash eeprom}} | | {{ http://www.auditeon.com/xyz/auditeon/20130317_213801.IMG_0723.1024x796.jpg?385x300 |TIAO adapter with flash eeprom}} |
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 ... ...
 </code> </code>
-This is rather confusing implemented in flashrom [[http://tracker.coreboot.org/trac/flashrom/changeset/1537|since May 16th 2012.]]. Measurements when using divisor=2 or with no divisor arguments, show a CLK signal of 30 MHz (The comments in the code say 2 is a default value) . Without looking into the source code, I presume the divisor implementation is not very consistent.+This is rather confusing implemented in flashrom [[http://tracker.coreboot.org/trac/flashrom/changeset/1537|since May 16th 2012]]. Measurements when using divisor=2 or with no divisor arguments, show a CLK signal of 30 MHz (The comments in the code say 2 is a default value). The code seems differently written than FTDI did.\\ \\ 
 To make measurements easier one can use the following one-liner, which repeats the command and activity on the bus. With this it is easier to analyze the cabling, termination and buffer circuit: To make measurements easier one can use the following one-liner, which repeats the command and activity on the bus. With this it is easier to analyze the cabling, termination and buffer circuit:
   cd $HOME/devel/flashrom; while true; do ./flashrom -p ft2232_spi:divisor=4,type=tumpa,port=A; done   cd $HOME/devel/flashrom; while true; do ./flashrom -p ft2232_spi:divisor=4,type=tumpa,port=A; done
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 ^ {{ http://www.auditeon.com/xyz/auditeon/10.RS_90.RL_OO.flashrom_jtag_clk.JPG?372x300 |RS=105, RL=∞}} ^ ^ {{ http://www.auditeon.com/xyz/auditeon/10.RS_90.RL_OO.flashrom_jtag_clk.JPG?372x300 |RS=105, RL=∞}} ^
 |  Real clk signal\\ RS=105 Ohm\\ No termination\\ JTAG cable length: 20cm  | |  Real clk signal\\ RS=105 Ohm\\ No termination\\ JTAG cable length: 20cm  |
 +The LVC16T245 buffer is causing a delay of about 6ns for the CLK signal.
 ===== Links and information ===== ===== Links and information =====
   * [[http://blog.csdn.net/imalex/article/details/6719614]]   * [[http://blog.csdn.net/imalex/article/details/6719614]]
software/linux/jtag.1368916824.txt.gz · Last modified: 2013/05/19 00:40 by admin